Diffusion of renewable energy technologies: barriers and stakeholders' perspectivesREDDY, Sudhakar; PAINULY, J. P.Renewable energy. 2004, Vol 29, Num 9, pp 1431-1447, issn 0960-1481, 17 p.Article

Design-for-testability to achieve complete coverage of delay faults in standard full scan circuitsPOMERANZ, Irith; REDDY, Sudhakar M.Journal of systems architecture. 2001, Vol 47, Num 3-4, pp 357-373, issn 1383-7621Article

Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan CircuitsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 10, pp 1907-1911, issn 1063-8210, 5 p.Article

Transparent-Segmented-Scan without the Routing Overhead of Segmented-ScanPOMERANZ, Irith; REDDY, Sudhakar M.Journal of low power electronics (Print). 2011, Vol 7, Num 2, pp 245-253, issn 1546-1998, 9 p.Article

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based TestsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2010, Vol 18, Num 2, pp 333-337, issn 1063-8210, 5 p.Article

Functional Broadside Tests with Minimum and Maximum Switching ActivityPOMERANZ, Irith; REDDY, Sudhakar M.Journal of low power electronics (Print). 2008, Vol 4, Num 3, pp 429-437, issn 1546-1998, 9 p.Article

A built-in self-test method for diagnosis of synchronous sequential circuitsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2001, Vol 9, Num 2, pp 290-296, issn 1063-8210Article

Resolution of Diagnosis Based on Transition FaultsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 1, pp 172-176, issn 1063-8210, 5 p.Article

Broadside and Functional Broadside Tests for Partial-Scan CircuitsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 6, pp 1104-1108, issn 1063-8210, 5 p.Article

Fixed-State Tests for Delay Faults in Scan DesignsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 1, pp 142-146, issn 1063-8210, 5 p.Article

On Functional Broadside Tests With Functional Propagation ConditionsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 6, pp 1094-1098, issn 1063-8210, 5 p.Article

Static Test Data Volume Reduction Using Complementation or Modulo-M AdditionPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 6, pp 1108-1112, issn 1063-8210, 5 p.Article

Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point InsertionPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 7, pp 931-936, issn 1063-8210, 6 p.Article

Reducing the Storage Requirements of a Test Sequence by Using One or Two Background VectorsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 10, pp 1755-1764, issn 1063-8210, 10 p.Article

Selection of a Fault Model for Fault Diagnosis Based on Unique ResponsesPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2010, Vol 18, Num 11, pp 1533-1543, issn 1063-8210, 11 p.Article

Improving the stuck-at fault coverage of functional test sequences by using limited-scan operationsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2004, Vol 12, Num 7, pp 780-788, issn 1063-8210, 9 p.Article

Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan CircuitsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 2, pp 333-337, issn 1063-8210, 5 p.Article

Path Selection for Transition Path Delay FaultsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2010, Vol 18, Num 3, pp 401-409, issn 1063-8210, 9 p.Article

Autoscan : A scan design without external scan inputs or outputsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 9, pp 1087-1095, issn 1063-8210, 9 p.Article

Resynthesis of combinational logic circuits for improved path delay fault testability using comparison unitsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2001, Vol 9, Num 5, pp 679-689, issn 1063-8210Article

Robust Fault Models Where Undetectable Faults Imply Logic RedundancyPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2010, Vol 18, Num 8, pp 1230-1234, issn 1063-8210, 5 p.Article

Random Test Generation With Input Cube AvoidancePOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 1, pp 45-54, issn 1063-8210, 10 p.Article

Transition Path Delay Faults : A New Path Delay Fault Model for Small and Large Delay DefectsPOMERANZ, Irith; REDDY, Sudhakar M.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 1, pp 98-107, issn 1063-8210, 10 p.Article

Properties of maximally dominating faultsPOMERANZ, Irith; REDDY, Sudhakar M.Asian test symposium. 2004, pp 106-111, isbn 0-7695-2235-1, 1Vol, 6 p.Conference Paper

A postprocessing procedure of test enrichment for path delay faultsPOMERANZ, Irith; REDDY, Sudhakar M.Asian test symposium. 2004, pp 448-453, isbn 0-7695-2235-1, 1Vol, 6 p.Conference Paper